As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Storage devices for information handling systems include hard disk drives (HDDs) and solid state drives (SSDs). Current HDD and SSD storage devices typically utilize a serial-based external interface, such as serial ATA (SATA), to connect internal read and write circuitry of the storage device to an information handling system serial data bus. Such storage devices also typically include serializer/deserializer physical layer circuitry (SerDes PHY) to convert between an internal parallel data bus within the storage device and the external serial data bus of the storage device. During storage device development and manufacture, SerDes PHY circuitry is characterized to ensure compliance with electrical specifications. SerDes characterization is important, for example, in the case of enterprise server development process which depends on server manufacturer teams working together to ensure a server product is developed and delivered robustly and timely. Uncertainty is added to the server development process when server manufacturer teams work with different external silicon vendors who use different SerDes PHYs. Typically, a server manufacturer provides an electrical specification which external silicon vendors are supposed to meet. When a silicon part fails to meet the manufacturer's electrical requirements, it is usually not caught by internal manufacturer screening due to limited testing and resource constraints. A random screening process is very cumbersome and involves a lot of work as well. Moreover, there is also a lot of variation between measurement to measurement due to human error, variation in hardware equipment and software, and other variants that complicate screening to verify silicon compliance with electrical specifications.
Characterization of settings for SerDes PHY circuitry is a complex and labor-intensive task that involves designing and constructing proper test equipment such as load boards and test cards, as well as ensuring that proper silicon samples are collected for testing. Current common practice to characterize PHY today is to mount the SerDes PHY circuitry on a test board with connectors that go into a high bandwidth scope (HBWS). Challenges incurred with the approach include a huge effort in terms of time and manual work, sensitivity to torquing and mating, repeatability is dependent on hardware equipment and software, and wear and tear on hardware. Thus, actual testing of individual circuit components is a complex and time-consuming process. To measure and characterize SerDes PHY de-emphasis (or equalization), jitter and voltage swing in a laboratory for each and very storage device is not only time consuming but also inefficient as it is not practically possible to test and characterize all storage device drives in the available time due to permutations that include different storage device and silicon vendors, different drive part numbers, different firmware revisions etc.
FIG. 9 illustrates conventional integrated SerDes PHY circuitry 900 such as used in a storage device of an information handling system. As shown, SerDes PHY circuit 900 includes separate transmitter circuitry 912 and receiver circuitry 914 integrated on the same semiconductor integrated circuit chip that operate independently of each other to transmit and receive data, respectively, across a SATA serial data bus 950 of the information handling system that is external to the chip. The separate transmitter and receiver circuits 912 and 914 of conventional SerDes PHY circuit 900 do not exchange data with each other on chip and are not connected on chip to exchange data between each other. Rather, the separate SerDes transmitter circuitry 912 serializes parallel advanced technology attachment (ATA) data from the storage device and transmits the SATA serial data off chip to other separate components of the information handling system (e.g., such as to a platform controller hub “PCH”) across an external transmit channel 913 of the serial data bus 950. The separate SerDes receiver circuitry 914 receives off chip serial SATA data from the other separate components of the information handling system across an external receive channel 915 of the serial data bus 950, and de-serializes the received serial data to produce ATA data for use by the storage device as shown.
In FIG. 9, an on-chip “digital eye” monitor 901 is integrated within the separate receiver circuitry 914 of the conventional SerDes PHY circuit 900, and is used to observe receive-side serial SATA data received from off chip by the SerDes receiver side circuitry 914 from separate information handling system components across the external receive channel 915 of the serial data bus 950. The on-chip digital eye 901 estimates the digital signal eye of the incoming received serial data signal after equalization by components of the receive side circuitry 914, and outputs the on-chip digital eye for display on an external display device so that performance of the SerDes receive side circuitry may be evaluated during testing. In this approach, the digital signal eye of the receive signal is estimated by shifting the phase rotators left and right until failure occurs, and also by shifting the voltage offset up and down.